XMU0

Look back at introductory MU0 lab exercise 4.3. You are encouraged to single step the ``MU0 - CPU Visual'' window to see the steps described above. See figure 5 - the thicker lines represent the parts of the buses that are active at this step in the execution of the current instruction, MAR is ADDR, DOUT is WRITE, and DIN is READ.

  

Figure 5: XMU0

CS1211 gives an alternative implementation of MU0 in much more detail. It is based on optimising memory activity, as it is usually slower than the CPU.