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Subsections

Instruction Execution on MU0

Instruction Execution on MU0

Computer Architecture

The part of the design visible to the user. The architecture of MU0 consists of:

See figure 1.

Figure 1: The basic MU0 architecture, with the visible registers ACC & PC
\begin{figure}\setlength{\unitlength}{1cm}\begin{picture}(16,8)
\thicklines\put(...
...XBUS
% put(4,1.5)\{ vector(0,-1)\{0.5\}\} % PC -> XBUS
\end{picture}\end{figure}

Implementation

An architecture can have more than one implementation, depending on other factors (technology, speed, price, power consumption etc.). We are going to look at a cheap, simple implementation.

For each instruction in turn, the implementation must:

We need extra registers, invisible to the user, e.g. to hold the current instruction while it is being decoded, and to communicate with the memory. See figure 2.

Figure 2: MU0 + invisible registers
\begin{figure}\setlength{\unitlength}{1cm}\begin{picture}(16,8)
\thicklines\put(...
...XBUS
% put(4,1.5)\{ vector(0,-1)\{0.5\}\} % PC -> XBUS
\end{picture}\end{figure}

ACC operations: the detailed steps to obey ADD, SUB, LDA & STO

ADD and SUB require the use of an Arithmetic Unit (often generically known as an Arithmetic & Logic Unit - ALU). To minimise the number of connections to the ACC, we also use the ALU for LDA and STO. Each of these 4 operations can be performed by a series of steps, which turn out to be very similar from one operation to the next, and can be summarised by the following table, listing the steps in the order they are obeyed:

ADD SUB LDA STO  
        send operand-location $\Rightarrow$ memory
$\surd$ $\surd$ $\surd$   read memory
        copy operand from memory $\Rightarrow$ ALU
$\surd$ $\surd$   $\surd$ copy ACC contents $\Rightarrow$ALU
+ - $\Rightarrow$ $\Rightarrow$ perform action in ALU
        ($\Rightarrow$: copy input to output)
$\surd$ $\surd$ $\surd$   ALU result $\Rightarrow$ ACC
        send operand-location $\Rightarrow$ memory
      $\surd$ ALU result $\Rightarrow$ memory
        write memory
See figure 3.

Figure 3: MU0 + ACC operations
\begin{figure}\setlength{\unitlength}{1cm}\begin{picture}(16,8)
\thicklines\put(...
...XBUS
% put(4,1.5)\{ vector(0,-1)\{0.5\}\} % PC -> XBUS
\end{picture}\end{figure}

This is not needed for the 4 operations described above, but for JGE and JNE we need to be able to test the current value in the ACC against the appropriate condition ($\ge$0 or $\ne$0) and let the control unit know if the result is true or false - maybe we could do this in the ALU as well, or maybe there is some extra hardware directly attached to the ACC.

PC operations, including the detailed steps to obey JMP, JNE & JGE

As mentioned above, we have to fetch each instruction, which means:

For JMP instructions, and JNE and JGE instructions when the test condition is true, we have to:

To do these actions, we could have another set of connections to memory and another adder. However, to simplify the hardware we can instead link the PC register to the existing ALU and through it to the memory. See figure 4.

Figure 4: MU0 + PC operations
\begin{figure}\setlength{\unitlength}{1cm}\begin{picture}(16,8)
\thicklines\put(...
...C -> XBUS
\put(4,1.5){\vector(0,-1){0.5}} % PC -> XBUS
\end{picture}\end{figure}

The STP instruction simply has to stop the next instruction being fetched.

MU0

In the introductory MU0 lab, in exercise 4.3, you are encouraged to single step the ``MU0 - CPU Visual'' window to see the steps described above. See figure 5 - the thicker lines represent the parts of the buses that are active at this step in the execution of the current instruction, MAR is ADDR, DOUT is WRITE, and DIN is READ. (The version of the simulator you are using actually uses different colours to indicate the active and inactive parts.)

Figure 5: MU0 CPU visual window
\includegraphics[width=15cm]{xmu0_cpu.ps}

CS1211 gives an alternative implementation of MU0 in much more detail. It is based on optimising memory activity, as it is usually slower than the CPU.


next up previous
Next: Numbers and Characters Up: ho Previous: MU0 - a simple
Pete Jinks 2003-09-25