Conclusion

This paper presented an overview of the design principles of an application representation that can support an integrated performance modeling environment for large-scale parallel systems. This representation is based on a task graph abstraction, and is designed to:

• provide a common source of workload information for different modeling paradigms including analytical models, simulation models and measurement, and
• to be generated automatically or with minimal user intervention, using parallelizing compiler technology.

The dHPF compiler has been extended to construct the task graph representation automatically for MPI programs generated by the dHPF compiler from an HPF source program. The compiler-generated static task graph has been used successfully to obtain very substantial improvements to the state-of-the-art of parallel simulation of message passing programs.

In our ongoing work, we aim to explore other uses of the compiler-synthesized task graph representation. We are integrating the representation into the POEMS environment where it will form an application-level model component within an overall model. The task graphs have already been interfaced with the parallel simulator MPI-Sim for the work referred to above. We also aim to integrate the task graph representation with an execution driven processor simulator to model individual task performance on future systems. The processor simulation model and the message-passing simulation model could then be combined; in fact, the task graph representation provides a common representation that makes it straightforward to combine modeling techniques in this manner. If successful, we believe that this work would lead to the first comprehensive and fully automatic performance prediction capability for very large-scale parallel applications and systems.