My core expertise is in the areas of on-chip interconnect analysis and design, 3-D integration, physical design issues for on-chip networks, and other design issues in VLSI. A past and successful research outcome - called the "Rochester Cube" - is shown in the figure on the left, which is a three-tier prototype circuits designed my PhD at the University of Rochester. My role within APT is to develop new design methodologies and techniques that reinforce the performance of the envisioned processor architectures. These methods primarily target both off-chip and on-chip communication among the processor chips as well as innovative system integration approaches for improved performance. In addition, I am interested in exploring the potential of emerging technologies and nanoscale devices and assessing the benefits that these fundamental technological advancements can offer into the future processor architectures.
My primary research areas include
- Design methods for 3-D architectures of multi-core processors
- Design of 3-D clock distribution networks
- Analysis and design of 3-D power distribution networks
- Modeling and design of MTJ/CMOS circuits
- Efficient techniques for inter-tier communication in vertically integrated circuits
- Modelling of process, voltage, and temperature variations in 3-D circuits