Vasilis F. Pavlidis, PhD


Authored books

V. F. Pavlidis and E. G. Friedman, Three-Dimensional Integrated Circuit Design, Morgan Kaufmann Publishers, ISBN: 978-0-12-374343-5, 2009. Translated in Chinese by China Machine Press ISBN 978-7-111-43351-4.
V. F. Pavlidis, I. Savidis, and E. G. Friedman Three-Dimensional Integrated Circuit Design, 2nd Edition, Morgan Kaufmann Publishers, ISBN:978-0-12-41501-0.

    Book chapters

  1. V. F. Pavlidis and E. G. Friedman, “Physical and Interconnect Design Issues in 3-D Integration Technologies,” in VLSI-SOC: Design Methodologies for SoC and SiP, pp. 1-21, Dimitrios Soudris, Christian Piguet, and Ricardo Reis (eds.), Springer, ISBN: 978-3-642-12266-8, 2010.

  2. V. F. Pavlidis and E. G. Friedman, “Physical Analysis of 3-D Topologies for NoCs,” in 3D-Integration for NoC-based SoC Architectures, Abbas Sheibanyrad, Frederic Petrot, and Axel Jantsch (eds.), Springer, ISBN: 978-1-4419-7617-8, pp. 89-114, 2011.

  3. A. Strano, D. Ludovici, D. Bertozzi, V. F. Pavlidis, F. Angiolini, and M. Krstic, “The Synchronization Challenge,” in Designing Network-on-Chip Architectures in the Nanoscale Era, José Flich, and Davide Bertozzi (eds.), Chapman & Hall/CRC Press, ISBN: 978-1-4398-3710-8, pp. 175-234, 2011.
  4. Journals

  5. H. Kalargaris and V. F. Pavlidis, "Voltage scaling for 3-D ICs: When, how, and how much?" Microelectronics Journal, Vol. 69, pp. 35-44, September 2017.

  6. H. Xu, V. F. Pavlidis, X. Tang, W. Burleson, and G. De Micheli, "Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply Noise," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 21, No. 12, pp. 2226-2239, December 2013.

  7. S. Rahimian, V. F. Pavlidis, and G. De Micheli, "An Enhanced Design Methodology for Resonant Clock Trees," Journal of Low Power Electronics, Vol. 9, No. 2, pp. 198-206, August 2013.

  8. H. Xu, V. F. Pavlidis, and G. De Micheli, "Effects of Process Variations on 3-D Global Clock Distribution Networks," ACM Journal on Emerging Technologies in Computing Systems, Vol. 8, No. 3, Article 20, August 2012.

  9. S. Rahimian, V. F. Pavlidis, and G. De Micheli, "Inter-Plane Communication Methods for 3-D ICs," Journal of Low Power Electronics, Vol. 8, No. 2, pp. 170-181, April 2012.

  10. K. Siozios, V. F. Pavlidis, and D. Soudris, "A Novel Framework for Exploring 3-D FPGAs with Heterogeneous Interconnect Fabric," ACM Transactions on Reconfigurable Technology and Systems, Vol. 5, No. 1, pp. 4:1-4:23, March 2012.

  11. V. F. Pavlidis, I. Savidis, and E. G. Friedman, "Clock Distribution Networks for 3-D Integrated Circuits," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 19, No. 12, pp. 2256-2266, December 2011.

  12. V. F. Pavlidis and E. G. Friedman, "Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits," Proceedings of the IEEE, Special Issue on 3-D Integration Technologies, Vol. 97, No, 1, pp. 123-140, January 2009.

  13. V. F. Pavlidis and E. G. Friedman, "3-D Topologies for Networks-on-Chip," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 15, No. 10, pp. 1081-1090, October 2007 (included in the Top 25 Downloadable Manuscripts for 2009).

  14. V. F. Pavlidis and E. G. Friedman, "Timing Driven Via Placement Heuristics in 3-D ICs ," Integration the VLSI Journal, Vol. 41, No. 4, pp. 489-508, July 2008.
  15. Conferences

  16. I. Papistas and V. F. Pavlidis, "Contactless Inter-Tier Communication for Heterogeneous 3-D ICs," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2585-2588, May 2017.

  17. I. Papistas and V. F. Pavlidis, "Comparative Study of Crosstalk Noise Due to Inductive Links on Heterogeneous 3-D ICs," Proceedings of the IEEE MTT-S International Conference on Numerical Electromagnetic and Multiphysics Modeling and Optimization for RF, Microwave, and Terahertz Applications, pp. 314-316, May 2017.

  18. K. Maragos, G. Lentaris, K. Siozios, D. Soudris, and V. F. Pavlidis, "Application Performance Improvement By Exploiting Process Variability On FPGA Devices," Proceedings of the Design, Automation, and Test Conference in Europe, pp. 452-457, March 2017.

  19. H. Kalargaris, Yi-Chung Chen, and V. F. Pavlidis, "STA Compatible Backend Design Flow for TSV-based 3-D ICs," Proceedings of the IEEE International Symposium on Quality Electronic Design, pp. 186-191, March 2017.

  20. S. Ladenheim, Y.-C. Chen, M. Mihajlovic, and V. F. Pavlidis, "IC Thermal Analyzer for Versatile 3-D Structures Using Multigrid Preconditioned Krylov Methods," Proceedings of the ACM/IEEE International Conference on Computer-Aided Design, November 2016.

  21. H. Kalargaris, J. Goodacre, and V. F. Pavlidis, "Advanced Circuit Interface for Systems with Multiple Voltage Domains," Proceedings of the IEEE International Ph.D. Research in Microelectronics and Electronics Conference, pp. 1-4, June 2016.

  22. I. Papistas and V. F. Pavlidis, "Crosstalk Noise Effects of On-Chip Inductive Links on Power Delivery Networks," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1938-1941, May 2016.

  23. I. Papistas and V. F. Pavlidis, "Inter-Tier Crosstalk Noise on Power Delivery Networks for 3-D ICs with Inductively-Coupled Interconnects," Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI, pp. 257-262, May 2016.

  24. I. Papistas and V. F. Pavlidis, "Bandwidth-to-Area Comparison of Through Silicon Vias and Inductive Links for 3-D ICs," Proceedings of the IEEE European Conference on Circuit Theory and Design, August 2015.

  25. H. Kalargaris and V. F. Pavlidis, "Interconnect Design Tradeoffs for Silicon and Glass Interposers," Proceedings of the IEEE International Conference on New Circuits and Systems, pp. 77-80, June 2014.

  26. P. W. Nutter, V. F. Pavlidis, and J. Pepper, "Efficient Teaching of Digital Design with Automated Assessment and Feedback," Proceedings of the European Workshop on Microelectronics Education, pp. 203-207, May 2014.

  27. S. Bobba, P.-E. Gaillardon, C. Seiculescu, V. F. Pavlidis, and G. De Micheli, "3.5-D Integration: A Case Study," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2087-2090, May 2013.

  28. S. Rahimian, V. F. Pavlidis, and G. De Micheli, "Low-Power Clock Distribution Networks for 3-D ICs," Proceedings of the Convention of Electrical and Electronics Engineers in Israel, November 2012.

  29. V. F. Pavlidis, H. Xu, and G. De Micheli, "Enhanced Wafer Matching Heuristics for 3-D ICs," Proceedings of the IEEE European Test Symposium, pp. 178, May 2012.

  30. H. Xu, V. F. Pavlidis, W. Burleson, and G. De Micheli, "The Combined Effect of Process Variations and Power Supply Noise on Clock Skew and Jitter," Proceedings of the IEEE International Symposium on Quality Electronic Design, pp. 322-329, March 2012.

  31. C. Zhang, V. F. Pavlidis, and G. De Micheli, “Voltage Propagation Method for 3-D Power Grid Analysis,” Proceedings of the Conference on Design, Automation, and Test, in Europe, pp. 844-847, March 2012.

  32. S. Rahimian, V. F. Pavlidis, and G. De Micheli, "Design of Resonant Clock Dostribution Networks for 3-D Integrated Circuits," Proceedings of the Power, Timing Modeling, Optimization, and Simulation Workshop, pp. 267-277, September 2011.

  33. G. De Micheli, V. F. Pavlidis, D. Atienza, and Y. Leblebici, "Design Methods and Tools for 3D Integration," Proceedings of the VLSI Technology Symposium, pp. 182-183, June 2011.

  34. H. Xu, V. F. Pavlidis, and G. De Micheli, "Skew Variability in 3-D ICs with Multiple Clock Domains," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2221-2224, May 2011.

  35. I. Savidis, V. F. Pavlidis, and E. G. Friedman, "Clock Distribution Models of 3-D Integrated Systems," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2225-2228, May 2011.

  36. H. Xu, V. F. Pavlidis, and G. De Micheli, “Analytical Heat Transfer Model for Thermal Through-Silicon Vias,” Proceedings of the Conference on Design, Automation, and Test, in Europe, pp. 395-400, March 2011.

  37. I. Tsioutsios, V. Pavlidis, and G. De Micheli, “Physical Design Tradeoffs in Power Distribution Networks for 3-D ICs,” Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, pp. 435-438, December 2010.

  38. V. Pavlidis, H. Xu, I. Tsioutsios, and G. De Micheli, “Synchronization and Power Integrity Issues in 3-D ICs,” Proceedings of Asia Pacific Conference on Circuits and Systems, pp. 536-539, December 2010.

  39. S. K. Bobba, A. Chakraborthy, O. Thomas, P. Batude, V. Pavlidis, and G. De Micheli, “Performance Analysis of 3-D Monolithic Integrated Circuits,” Proceedings of the IEEE International 3D System Integration Conference, November 2010.

  40. H. Xu, V. F. Pavlidis, and G. De Micheli, “Process-Induced Skew Variation for Scaled 2-D and 3-D ICs,” Proceedings of the System Level Interconnect Prediction Workshop, pp. 17-24, June 2010.

  41. H. Xu, V. F. Pavlidis and G. De Micheli, “Repeater insertion for Two-Terminal Nets in Three-Dimensional Integrated Circuits,” Proceedings of the International ICST Conference on Nano-Networks, pp. 141-150, October 2009.

  42. V. F. Pavlidis and G. De Micheli, “Power Distribution Paths for 3-D ICs,” Proceedings of the International ACM Great Lakes Symposium on Very Large Scale Integration, pp. 263-268, May 2009.

  43. K. Siozios, V. F. Pavlidis, and D. Soudris, “A Software-Supported Methodology for Exploring Interconnection Architectures Targeting 3-D FPGAs,” Proceedings of the Design, Automation, and Test Conference in Europe, pp. 172-177, April 2009.

  44. V. F. Pavlidis, I. Savidis, and E. G. Friedman, “Clock Distribution Architectures for 3-D SOI Integrated Circuits,” Proceedings of the IEEE International Silicon-on-Insulator Conference, pp. 111-112, October 2008.

  45. V. F. Pavlidis, I. Savidis, and E. G. Friedman, “Clock Distribution Networks for 3-D Integrated Circuits,” Proceedings of the IEEE International Conference on Custom Integrated Circuits, pp. 651-654, September 2008 (An AMD/CICC Student Scholarship Award was awarded to this paper).

  46. K. Siozios, K. Sotiriadis, V. F. Pavlidis, and D. Soudris, “A Software-Supported Methodology for Designing High-Performance 3D FPGA Architectures,” Proceedings of the International Conference on VLSI-SoC, pp. 54-59, October 2007.

  47. K. Siozios, K. Sotiriadis, V. F. Pavlidis, and D. Soudris, “Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support,” Proceedings of the IEEE International Conference on Field Programmable Logic and Applications, pp. 652-655, August 2007.

  48. V. F. Pavlidis and E. G. Friedman, “Three–Dimensional (3-D) Topologies for Networks-on-Chip,” Proceedings of the IEEE International System on Chip Conference, pp. 285-288, September 2006.

  49. V. F. Pavlidis and E. G. Friedman, “Via Placement for Minimum Interconnect Delay in Three-Dimensional (3-D) Circuits,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 4587-4590, May 2006.

  50. V. F. Pavlidis and E. G. Friedman, “Interconnect Delay Minimization through Interlayer Via Placement in 3-D ICs,” Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration, pp. 20-25, April 2005.

  51. D. Soudris, K. Sgouropoulos, K. Tatas, V. F. Pavlidis, and A. Thanailakis, “A Methodology for Implementing FIR Filters and CAD Tool Development for Designing RNS-Based Systems,” Proceedings of the International Symposium on Circuits and Systems, pp. 129-132, May 2003.

  52. D. Soudris, V. F. Pavlidis, and A. Thanailakis, “Designing Low-Power Energy Recovery Adders Based On Pass Transistor Logic,” Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, pp. 777-780, September 2001.

Other articles (non-peer reviewed)

La 3D révolutionne le monde des microprocesseurs, Science & Vie, No. 1094, p. 54, November 2008.
University of Rochester (2008, September 17). 3-D Computer Processor: 'Rochester Cube' Points Way To More Powerful Chip Designs. Science Daily.